基于Nios II的伪随机序列信号发生器IP核设计

详细信息

Design of IP Core of Signal Generator of Pseudo-random Sequence Based on Nios II

Electronics and Information College of Yangtze University, Jingzhou 434023, China

摘要: 根据Nios II嵌入式系统的Avalon总线规范，提出了一种伪随机序列信号发生器IP核的设计方法，详细介绍了IP核的硬件和软件设计。该方法采用自定制组件的软硬件协同设计，实现了阶次与码字时长可调的伪随机序列信号发生器IP核设计。在可控震源信号发生器设计中对IP核进行验证，证明了其可行性和正确性。
- 伪随机码 /
- 信号发生器 /
- Nios II /
- SOPC Builder /
- Avalon总线 /
- IP核
Abstract: The paper put forward a design method of IP core of signal generator of pseudo-random sequence according to Avalon bus specification of Nios II embedded system, and introduced hardware and software designs of the IP core in details. The method uses collaborative design of software and hardware of custom component to achieve IP core design of signal generator of pseudo-random sequence with adjusted code length and order. Its feasibility and correctness were proved in design of controlled vibrating signal generator.
- pseudo-random sequence, signal generator, Nios II, SOPC Builder, Avalon bus, IP core